1. Field of the Invention
The present invention relates to a charged beam drawing apparatus and method thereof.
2. Description of the Related Art
In recent years, as semiconductor devices are complicatedly structured, a charged particle beam (for example, an electron beam) has been used to expose a resist which is applied on a wafer.
When a wafer is divided into a plurality of pieces in a chip size, the surface of the wafer includes a chip area in which to-be-manufactured chips (device chip) are formed and a peripheral area in which peripheral chips (not to be manufactured owing to their incompleteness of the form) are formed.
An area of a single peripheral chip is smaller than that of a device chip. Therefore, if an electron beam is irradiated onto the peripheral area based on the same exposure data as the chip area, the electron beam may possibly be irradiated onto a wafer holder for holding the wafer.
If the electron beam is irradiated onto the wafer holder, oil mist composed of a very small amount of organic matter is printed on a wafer holder, then an insulating film is formed on the wafer holder. Such insulating film is charged up when irradiating the electron beam onto the following wafer, particularly when exposing the peripheral area. Charging up the insulating film brings about drift of the electron beam. Once the irradiation position of the electron beams is drifted, an irradiation position of the electron beam deviates from its appropriate position. Then, the exposure area of the resist also deviates from an appropriate position, resulting in the resist being patterned inaccurately.
Disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H8-51052 is a technique for overcoming the above-described problems. According to the technique disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H8-51052, peripheral chips are divided into a plurality of smallest areas onto which the electron beam can still be irradiated, when exposing a peripheral area. The electron beam is controlled not to be irradiated onto the wafer holder and to expose only the peripheral chips. In the exposure of the peripheral area, a positive type resist is applied on the wafer, and the electron beams is irradiated onto the entire peripheral area, so as to remove the resists from the peripheral area.
However, in the technique disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H8-51052, there is found such a problem as shown below.
Since the peripheral chips formed in the peripheral area can not be manufactured, a degree of accuracy of the irradiation position and exposure amount when exposing the peripheral area may be lower than a degree thereof when exposing the chip area.
However, according to the above-described technique, the peripheral chips are only divided into a plurality of small areas in order to irradiate the electron beam onto the peripheral chips rather than the onto the wafer holder. Thus, a problematic matter arises in that the electric power is wastefully consumed, and that the throughput of to-be-manufactured semiconductor devices is low.
If the resist on the peripheral area is removed as described above, the side wall of the resist formed in the chip area is exposed. Thus, the side wall of the resist formed in the chip area may be etched, in the etching performed after the resist is removed from the peripheral area.
If the side wall of the resist formed in the chip area is unnecessarily etched as described above, low yield of to-be-manufactured semiconductor devices may problematically be realized.